Digital Systems Testing And Testable Design Solution |top| Jun 2026

Engineers cannot easily test for every possible physical defect (like a microscopic crack in a wire). Instead, they use mathematical to simulate how defects change logic behavior.

The chip executes self-test without external stimuli:

This is the most common approach. It involves replacing standard flip-flops with "scan flip-flops" that can be linked into a long shift register. In "test mode," data is shifted in to set every internal state, the system runs for one clock cycle, and the results are shifted out for inspection.

With clock frequencies exceeding 2-5 GHz, timing faults are as critical as stuck-at faults. is used:

Every I/O pin on a compliant chip has a (a small register) placed between the core logic and the pin pad. These cells are daisy-chained into a boundary scan register around the periphery of the chip.

Dedicated circuitry designed to test embedded RAM and ROM. It runs specific algorithmic patterns (like March tests) to detect memory cell leaks, shorts, and coupling faults. Boundary Scan (IEEE 1149.1 / JTAG)

The relentless pursuit of Moore's Law has delivered miraculous density and performance. But a 100-billion-transistor chip with 99.9% manufacturing yield still contains 100 million defective transistors if untested. The gap between what we can design and what we can manufacture reliably is bridged exclusively by .

a specific test vector to set the internal state of the entire chip (Controllability).

The insight is brilliant in its simplicity: Replace every standard flip-flop (or most of them) with a and connect them into one or more long shift registers called scan chains .

BIST moves the external testing equipment directly onto the chip itself. This allows the chip to test itself without relying heavily on expensive external Automated Test Equipment (ATE).

The dominant solution for sequential circuits is scan testing. During normal operation, flip-flops act as state-holding elements. In test mode, these same flip-flops are reconfigured into a giant shift register, or "scan chain." Test vectors are shifted in serially, setting every internal flip-flop to a known state in just a few hundred clock cycles. After a single functional clock pulse captures the circuit's response, the result is shifted out for comparison. This elegantly converts a complex sequential test problem into a simpler combinational one.

The fundamental challenge of digital testing is summarized by two metrics: